Intel and Spain invest 400 400 M in R&D of open source RISC-V microprocessor

Spanish government and Intel With plans to invest up to 400 million euros over 10 years to set up a new joint laboratory Barcelona Supercomputing Center – Centro Nacional de Supercomputación (BSC-CNS). One of the main objectives will be to design a microprocessor with technology based on the RISC-V open architecture for use in future JetScale supercomputers.

Zettascale aims to break the supercomputer’s barrier 1021 Activity per second, 1000 times faster than today’s most powerful supercomputers.

This joint laboratory will help Europe become self-sufficient in these types of chips that can be used in the design of self-propelled cars or devices for the application of artificial intelligence. The announcement was made at Europe’s largest High Performance Computing (HPC) conference in Hamburg, Germany. The joint laboratory will receive up to 400 million euros in 10 years of investment. These funds will come from Intel and the Spanish government through the PERTE chip as part of a recovery, conversion and resilience plan (see our Articles)

We are delighted that Intel has jointly chosen BSC to create a research lab that will be a world leader in chip design. One of the objectives will be to integrate advanced European supercomputers, such as MareNostrum 6 and many others around the world, into this laboratory in 5 years. Mateo Valero, director of BSc-CNS, said.

High-performance computing is the key to solving the world’s most difficult problems, and at Intel, we have an ambitious goal for HPC to move into the zettascale era. The Barcelona Supercomputing Center shares our vision, with an equal emphasis on sustainability and an open approach. We are delighted to be partnering with them to start this adventure Jeff McVee, vice president and general manager of Intel’s SuperCompute Group, added.

Europe still relies on microprocessors for supercomputers, designed and marketed by most American companies and manufactured in countries such as Taiwan and South Korea. The purpose of the joint laboratory will be the design of ultra-high-capacity chips for supercomputers, autonomous vehicles and devices for the application of artificial intelligence.

The design of the RISC-V open-source architecture began in 2010 at UC Berkeley with the need to reduce the growing complexity of microprocessor instruction storage and limit heavy reliance on third countries.

New processor designed by joint laboratory BSc-CNS And Intel will lead the development of new technologies, such as future JetScale computers. These supercomputers will break the barrier of 1021 operations per second, which is 1000 times faster than today’s most powerful supercomputers. Zettascale supercomputers will thus be able to solve problems that are currently unthinkable or difficult to solve. For example, they would be the key to creating the Earth’s digital twins that mimic climate models with high precision to explore the effects of global warming; The digital twins of the human body, which will help prevent and treat diseases like cancer; Whether the model of the universe we are currently using is accurate; And provides answers to fundamental questions such as the contraction or expansion of the universe.

The joint laboratory is expected to create 300 new highly skilled jobs and will be an innovation center that will attract new international investment. The laboratory will be located on the north campus of the Polytechnic University of Catalonia, which also has BSc-CNS facilities. BSC-CNS collaboration with Intel started in 2011 Since then, the two companies have worked together to accelerate research and development in high-performance computing.

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